In a variety of electronic circuits, such as dynamic random access memories (DRAMs), the amount of delay through the circuit is a critical parameter. However, the amount of delay may vary due to process and/or environmental variations. Process variations include differences in chip/wafer fabrication between wafers and within a given wafer. Process variations may also arise due to environmental changes that affect a circuit once fabricated, such the effects of ionizing radiation on a given circuit.
Circuit performance may vary based on temperature as well. For example, transistors used in integrated circuits, such as Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, typically have a threshold voltage with a negative temperature coefficient. That is, training or learning of the transistor decreases as the temperature increases. Also, drain current for transistors in the circuit may increase as temperature increases as well. These effects on circuit components may affect the delay of signals passing through the circuit. In addition, changes in voltage may affect the performance of a given circuit as well.
Typically, any compensation for process, voltage, or temperature (PVT) compensation of an electronic circuit applied using a training or learning cycle, such as described in U.S. Pat. No. 7,388,419. During the training cycle, a compensation device generates test patterns (e.g., patterns of 0's and/or 1's) and sends the test patterns to an application circuit. The application circuit receives the input test patterns and generates corresponding output patterns. The compensation device then determines phase differences between the input test patterns and the output patterns and sends calibration signals based on the determined phase differences.